1. Field of the Invention
This invention relates to an electronic logic driver circuit. More specifically, this invention relates to reducing power consumption of electronic logic circuits and the conditioning of signals within electronic logic circuits.
An electronic circuit consumes power in various ways. In particular, power is consumed when input signals to elements of the circuit change state. A contribution to this power consumption occurs because of the charging and discharging of parasitic capacitance associated with the input signals to circuit elements and with wires connecting these input signals to signal drivers. Power dissipation does not occur in the parasitic capacitance itself, but in the output resistance of the signal drivers. A modem digital integrated circuit (IC) typically drives a large number of off-chip signals, which, whilst having high capacitance loading, operate at a relatively low frequency and thus consume a significant (but nevertheless small) portion of the total power consumption of the IC. ICs also include many global on-chip signals, such as clock signals or address lines, which traverse the entire chip driving many internal inputs. These have high parasitic capacitance but in addition operate generally at very high speed. Consequently, such signals can consume a moderately high portion of the total power consumption of the IC. A driver circuit that reduces power dissipation capable of driving such on-chip signals at a speed comparable to conventional on-chip drivers would therefore be highly desirable.
2. Summary of the Prior Art
Referring to the drawings, FIG. 1 shows, for the purpose of illustration, a conventional CMOS IC inverter driver 10 that furnishes a driver output signal VD to an interconnect 12, which in turn furnishes interconnect output signal VO to a load 14. Where the driver 10 is used as an on-chip driver, the load 14 is typically constituted by inputs to further logic devices formed as part of the same IC and the interconnect 12 is formed in on-chip metallization layers. Due to their small dimensions, on-chip interconnects typically have low series inductance. Alternatively, where the driver 10 is used as off-chip driver, the load 14 is typically constituted by input pins to further IC's mounted on the same printed circuit board (PCB) and the interconnect 12 is constituted by a combination of lead-frame conductors within IC packages and conductors etched onto the PCB. Due to relatively large dimensions of PCB conductors, such interconnects have typically have appreciable series inductance.
The inverter driver 10 includes an NMOS transistor M1 serially connected to a PMOS transistor M2 between a positive supply rail VDD and a ground supply rail VSS. Since M1 is turned on by applying a positive voltage to its gate input and M2 is turned on by applying a ground potential to its gate input, normally only one of the two is conductive during steady-state conditions. Therefore, if the input signal VC is at a ‘low’ potential (i.e. near VSS potential) then the driver output signal VD is driven to a ‘high’ potential (i.e. near VDD potential), and conversely. During transitions of the input signal VC between high and low potentials, there is generally a brief period when both transistors M1 and M2 are simultaneously conductive.
In FIG. 2 there is shown a simplified electrical model of the circuit of FIG. 1. The output of the inverter driver 10 is modelled by a controllable switch SW in series with an output resistance R(ON). The output resistance represents the source-drain resistance of either transistor M1 or M2 in its ‘on’ condition. A capacitor C(IN) models the input (gate) capacitance of the transistors M1 and M2. The interconnect 12 is modelled by a series resistance RI and a series inductance L1 and a distributed capacitance CI. The distributed capacitance CI is typically smaller than the load capacitance CL so that, to a reasonable degree of accuracy, the distributed capacitance CI can be considered as forming part of load capacitance CL.
FIG. 3a shows how signals VD and VO in FIG. 1 typically change when an input signal VP is driven from ‘high’ to ‘low’ when the driver 10 is used as an on-chip driver. In this case, the current flow into load CL is effectively limited by the driver output resistance R(ON), so the driver output signal VD changes approximately exponentially from ‘low’ to ‘high’. Since the interconnect inductance and resistance are comparatively small, the conductor output signal VO is only slightly delayed and overshoot is negligible. FIG. 3b shows how signals VD and VO in FIG. 1 typically change when input signal VP is driven from ‘high’ to ‘low’ when the driver 10 is used as an off-chip driver. In this case, the current flow into load CL is effectively determined both by the driver output resistance R(ON) and the interconnect inductance LI. Hence, although the driver output signal VD begins a transition from ‘low’ to ‘high’ quite quickly, the interconnect inductance causes the interconnect output signal VO to change in a damped sinusoidal manner with some degree of overshoot.
On-chip signals are generally required to operate at very high speed, therefore a low value of R(ON) is needed. This is achieved by making the channel width of the drive transistors within the driver 10 quite large. This means that the input capacitance C(IN) of driver 10 may be as much as one third the value of load capacitance CL. For the case off-chip drivers, R(ON) typically is made much larger in relative terms to limit the speed of the transition and to reduce the ringing and overshoot that would otherwise occur due to the appreciable inductance of the interconnect. Nevertheless, there is typically some overshoot as shown in FIG. 3b. Since a larger R(ON) is desirable, the channel width of drive transistors within the driver 10 can be made much smaller for a given load capacitance when driver 10 is an off-chip driver. Therefore, in this case the input capacitance C(IN) of the driver 10 is quite small compared to load capacitance CL. In both cases, the energy drawn from the supply (ignoring that used in charging and discharging C(IN)) is approximately equal to CV2, where V is the potential between VDD and VSS and C is the numerical value of CL. Similar waveforms occur when the output goes from ‘high’ to ‘low’, but in this case there is no power is drawn from the VDD supply. Therefore, the power drawn from the VDD supply when the output is driven at a frequency f is on average equal to fCV2. Much of this power is dissipated in the driver output resistance R(ON). The power dissipation cannot be reduced merely by making the value of R(ON) smaller since the only effect would be to increase the amount of overshoot and ringing.
In WO-A-97/09783, the present applicant showed that the power dissipation, especially of off-chip drivers, can be reduced typically by 75% by harnessing, as an energy storage mechanism, the ringing that occurs when load 14 is driven via an appreciable inductance such as PCB interconnect inductance. This was accomplished by replacing the driver 10 by an alternative driver 18 as shown in FIG. 4, in which the driver output voltage changes from ‘low’ to ‘high’ and vice versa, through an intermediate voltage. An input signal VC to the driver 18 feeds a control circuit that generates control signals V5, V6 and V7, which in turn connect, to the gate electrodes of NMOS transistors M3 and M4 and a PMOS transistor M5 respectively. The drain connections of these transistors M3, M4 and M5 are all connected to the output VS of the driver 18. The transistors M3 and M5 can connect the output signal VS to VSS and VDD respectively whilst the transistor M4 can connect the output to an intermediate voltage VHH. Generally, the transistor M4 is designed to have a lower ‘on’ resistance than either of the transistors M3 or M5 (or M1 or M2 in FIG. 1 when the driver 10 is used as an off-chip driver). The output signal VS is also connected to the load 14 via a PCB interconnect 12, which has been modelled as an inductor LR.
FIG. 5 shows the waveform that would result if signals VS and VO have been previously charged to a steady state VSS potential by the transistor M3 having been turned on, but with the transistor M3 now being turned off. At time t1, the transistor M4 is turned on indefinitely. The output VS of the driver moves quickly to VHH potential. Because the transistor M4 has a low ‘on’ resistance, the voltage of the interconnect output signal VO overshoots VHH potential and reaches almost the potential of VDD, and thereafter rings sinusoidally with a resonant frequency f(r) given by Equation 1.1 below.
                              f          ⁡                      (            r            )                          =                  1                      2            ⁢            Π            ⁢                                          L                ⁢                                                                  ⁢                C                                                                        (        1.1        )            
The current passing through the transistor M4 alternates in direction and also causes a very small voltage drop across the transistor M4, causing the output voltage VS of the driver to deviate slightly from VHH potential. Since a small amount of power is dissipated in the transistor M4 and in the also in the various loss mechanisms associates with the load, the amplitude of oscillations gradually decreases.
FIG. 6 shows how, if the sinusoidal oscillation depicted in FIG. 5 can be arrested at time t2 (i.e. after half of one complete oscillation). The required transition of interconnect output signal VO can be achieved with very low power dissipation. The driver output signal VS is held at or near VHH potential until the interconnect output signal VO reaches a first maximum. Then the potential of the signal VS is raised to that of VDD by switching off the transistor M4 and switching on the transistor M5. FIG. 6 also shows the required sequence of control signals V5, V6 and V7 in response to the input V1 for LOW-to-HIGH and HIGH-to-LOW transitions. The driver 18 then furnishes an output signal VS in the form of a two-step rising or falling staircase. By exploiting resonance between the interconnect inductance LR and load CL, this allows the interconnect output signal VO to largely complete each conductor output transition while the VS signal is held at an intermediate level. This means that greatly reduced current is drawn from the power supply. This general technique will be called “staircase resonant” driving of capacitive loads in this specification.
The staircase resonant driver 18 is useful for driving off-chip signals that have a relatively slow rise time and have inherent series inductance sufficient to produce resonance. On-chip signals generally have low inductance but on-chip inductors (for example spiral trace inductors) could be explicitly provided to furnish the required resonance inductance. However, on-chip signals must generally be driven at a speed typically an order of magnitude faster than off-chip signals. The peak current flowing in the transistor M4 in FIG. 4 is therefore an order of magnitude higher driving an on-chip load capacitance compared with driving the same off-chip load capacitance so that the “ON” resistance of the transistor M4 is made an order of magnitude lower to achieve the same level of resonant overshoot. Of course, the “ON” resistance of the transistor M4 can be reduced by increasing its channel width; but after a point it requires an excessive power consumption to operate or switch transistor M4 due to its increased gate capacitance such that the overall power dissipation is increased contrary to the desired effect which is to decrease overall power dissipation.
The driver 18 is may be unsuitable for driving high-speed on-chip signals because the transistor M4 has an “ON” resistance that is too high in relation to the power taken to switch it on and off. This is partly because the maximum gate-source voltage applied to the transistor M4 between times t1 and t2 in FIG. 6 is only half of the power supply voltage and because the time of rise and fall of the control signal V is now similar to the desired conductor output rise/fall time and the average gate-source voltage is even lower. Furthermore, the control voltage V makes two transitions corresponding to each transition of the output. This further limits the channel width of the transistor M4 that can be used without leading to excessive power consumption.
There is therefore a desire to provide a driver circuit having the low power advantages of the driver 18 whilst being capable of driving on-chip signals at high speed.